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Job Description

Worked on full chip synthesis using Synopsys DC / Cadence RC compiler

Strong fundamentals of Timing constraints

Experience with Synopsys PrimeTime – Must

Worked on 90nm / 65 nm or below design timing closure

Understanding of Verilog/VHDL RTL constructs

Working knowledge of Layout tools – a plus point

Exposure to DDR2/3, high speed I/O timing Interface or similar – a plus point

TCL / Perl etc scripting

Good communication skill

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